Root causes confirmed from code audit: 1. DCache coherency: USB OTG FS reads physical SRAM while CPU writes through DCache. Fix: MPU Region 0 marks 512B aligned USB buffer struct non-cacheable (TEX=1, C=0, B=0) before HAL_PCD_Init(). DCache stays enabled globally. 2. IWDG ordering: safety_init() (IWDG start) deferred after all peripheral inits to avoid watchdog reset during mpu6000_calibrate() (~510ms blocking). DMA conflicts, GPIO conflicts, clock tree, and interrupt priorities all ruled out with evidence. Full findings documented in USB_CDC_BUG.md. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Description
SaltyLab self-balancing bot firmware (STM32F722)
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