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fix: CAN on GPIO 15/16, UART IO on 17/18 — actual hardware wiring

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Tee confirmed physical wiring on Waveshare ESP32-S3 board:
- GPIO 15 = CAN TX (SN65HVD230 TXD)
- GPIO 16 = CAN RX (SN65HVD230 RXD)
- GPIO 17/18 = inter-board UART to ESP32 IO

Previous configs (GPIO 2/1, 43/44) were spec assumptions that didn't
match the actual board wiring. GPIO 43/44 are internal to PCB, not
on the header where the transceiver is connected.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
Sebastien Vayrette 2026-04-20 12:17:39 -04:00
parent 330c2ab4fe
commit 8e66430c86
1 changed files with 10 additions and 14 deletions
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24
esp32s3/balance/main/config.h
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@ -11,25 +11,21 @@
* to IO2/IO1 when deploying this firmware. See docs/SAUL-TEE-SYSTEM-REFERENCE.md. * to IO2/IO1 when deploying this firmware. See docs/SAUL-TEE-SYSTEM-REFERENCE.md.
*/ */
/* ── Orin serial: CH343 USB-UART bridge (1a86:55d3 = /dev/ttyACM0 on Orin) ── /* ── Orin serial: USB Serial/JTAG (native USB, /dev/ttyACM0 on Orin) ── */
* Physical path: Orin USB → CH343 → GPIO 43 (TX) / GPIO 44 (RX).
* NOTE: lsusb on Orin shows ONLY CH343, not ESP32 native USB (303a:xxxx).
* USB Serial/JTAG is console-only — it is not the Orin↔ESP32 data path.
*/
#define ORIN_UART_PORT UART_NUM_0 #define ORIN_UART_PORT UART_NUM_0
#define ORIN_UART_BAUD 460800 #define ORIN_UART_BAUD 460800
#define ORIN_UART_TX_GPIO 43 /* ESP32 → CH343 RXD */ #define ORIN_UART_TX_GPIO 43 /* unused — Orin uses USB-CDC */
#define ORIN_UART_RX_GPIO 44 /* CH343 TXD → ESP32 */ #define ORIN_UART_RX_GPIO 44 /* unused — Orin uses USB-CDC */
#define ORIN_UART_RX_BUF 1024 #define ORIN_UART_RX_BUF 1024
#define ORIN_TX_QUEUE_DEPTH 16 #define ORIN_TX_QUEUE_DEPTH 16
/* ── VESC CAN TWAI (SN65HVD230 target GPIO 2/1 per bd-66hx design) ── /* ── Inter-board UART (ESP32 Balance ↔ ESP32 IO) ── */
* HARDWARE NOTE: SN65HVD230 transceiver must be physically wired to GPIO 2 #define IO_UART_TX_GPIO 17
* (TXD) and GPIO 1 (RXD). Old prototype wiring used GPIO 43/44 but those #define IO_UART_RX_GPIO 18
* pins are now committed to UART (CH343). Rewire required before CAN works.
*/ /* ── VESC CAN TWAI (SN65HVD230 on Waveshare header pins) ── */
#define VESC_CAN_TX_GPIO 2 /* ESP32 TWAI TX → SN65HVD230 TXD */ #define VESC_CAN_TX_GPIO 15 /* GPIO15 → SN65HVD230 TXD */
#define VESC_CAN_RX_GPIO 1 /* SN65HVD230 RXD → ESP32 TWAI RX */ #define VESC_CAN_RX_GPIO 16 /* GPIO16 ← SN65HVD230 RXD */
#define VESC_CAN_RX_QUEUE 32 #define VESC_CAN_RX_QUEUE 32
/* VESC node IDs — matched to bd-wim1 TELEM_VESC_LEFT/RIGHT mapping */ /* VESC node IDs — matched to bd-wim1 TELEM_VESC_LEFT/RIGHT mapping */