sl-firmware
291dd689f8
Archive STM32 firmware to legacy/stm32/: - src/, include/, lib/USB_CDC/, platformio.ini, test stubs, flash_firmware.py - test/test_battery_adc.c, test_hw_button.c, test_pid_schedule.c, test_vesc_can.c, test_can_watchdog.c - USB_CDC_BUG.md Rename: stm32_protocol → esp32_protocol, mamba_protocol → balance_protocol, stm32_cmd_node → esp32_cmd_node, stm32_cmd_params → esp32_cmd_params, stm32_cmd.launch.py → esp32_cmd.launch.py, test_stm32_protocol → test_esp32_protocol, test_stm32_cmd_node → test_esp32_cmd_node Content cleanup across all files: - Mamba F722S → ESP32-S3 BALANCE - BlackPill → ESP32-S3 IO - STM32F722/F7xx → ESP32-S3 - stm32Mode/Version/Port → esp32Mode/Version/Port - STM32 State/Mode labels → ESP32 State/Mode - Jetson Nano → Jetson Orin Nano Super - /dev/stm32 → /dev/esp32 - stm32_bridge → esp32_bridge - STM32 HAL → ESP-IDF docs/SALTYLAB.md: - Update "Drone FC Details" to describe ESP32-S3 BALANCE board (Waveshare ESP32-S3 Touch LCD 1.28) - Replace verbose "Self-Balancing Control" STM32 section with brief note pointing to SAUL-TEE-SYSTEM-REFERENCE.md TEAM.md: Update Embedded Firmware Engineer role to ESP32-S3 / ESP-IDF No new functionality — cleanup only. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
#ifndef PID_FLASH_H
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#define PID_FLASH_H
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#include <stdint.h>
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#include <stdbool.h>
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/*
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* pid_flash — persistent PID storage for Issue #531 (auto-tune).
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*
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* Stores Kp, Ki, Kd in the last 64 bytes of STM32F722 flash sector 7
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* (0x0807FFC0). Magic word validates presence of saved params.
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* Sector 7 is 128KB starting at 0x08060000; firmware never exceeds sector 6.
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*
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* Flash writes require an erase of the full sector (128KB) before re-writing.
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* The store address is the very last 64-byte block so future expansion can
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* grow toward lower addresses within sector 7 without conflict.
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*/
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#define PID_FLASH_SECTOR FLASH_SECTOR_7
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#define PID_FLASH_SECTOR_VOLTAGE VOLTAGE_RANGE_3 /* 2.7V-3.6V, 32-bit parallelism */
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/* Sector 7: 128KB at 0x08060000; store in last 64 bytes */
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#define PID_FLASH_STORE_ADDR 0x0807FFC0UL
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#define PID_FLASH_MAGIC 0x534C5401UL /* 'SLT\x01' — version 1 */
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typedef struct __attribute__((packed)) {
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uint32_t magic; /* PID_FLASH_MAGIC when valid */
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float kp;
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float ki;
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float kd;
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uint8_t _pad[48]; /* padding to 64 bytes */
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} pid_flash_t;
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/* ---- Gain schedule flash storage (Issue #550) ---- */
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/* Maximum number of speed-band entries in the gain schedule table */
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#define PID_SCHED_MAX_BANDS 6u
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/*
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* Sector 7 layout (128KB at 0x08060000):
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* 0x0807FF40 pid_sched_flash_t (128 bytes) — gain schedule record
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* 0x0807FFC0 pid_flash_t ( 64 bytes) — single PID record (existing)
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* Both records are written in a single sector erase via pid_flash_save_all().
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*/
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#define PID_SCHED_FLASH_ADDR 0x0807FF40UL
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#define PID_SCHED_MAGIC 0x534C5402UL /* 'SLT\x02' — version 2 */
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typedef struct __attribute__((packed)) {
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float speed_mps; /* velocity breakpoint (m/s) */
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float kp;
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float ki;
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float kd;
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} pid_sched_entry_t; /* 16 bytes */
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typedef struct __attribute__((packed)) {
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uint32_t magic; /* PID_SCHED_MAGIC when valid */
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uint8_t num_bands; /* valid entries (1..PID_SCHED_MAX_BANDS) */
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uint8_t flags; /* reserved, must be 0 */
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uint8_t _pad0[2];
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pid_sched_entry_t bands[PID_SCHED_MAX_BANDS]; /* 6 × 16 = 96 bytes */
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uint8_t _pad1[24]; /* total = 4+1+1+2+96+24 = 128 bytes */
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} pid_sched_flash_t; /* 128 bytes */
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/*
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* pid_flash_load() — read saved PID from flash.
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* Returns true and fills *kp/*ki/*kd if magic is valid.
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* Returns false if no valid params stored (caller keeps defaults).
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*/
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bool pid_flash_load(float *kp, float *ki, float *kd);
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/*
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* pid_flash_save() — erase sector 7 and write Kp/Ki/Kd (single-PID only).
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* Use pid_flash_save_all() to save both single-PID and schedule atomically.
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* Must not be called while armed (flash erase takes ~1s and stalls the CPU).
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* Returns true on success.
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*/
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bool pid_flash_save(float kp, float ki, float kd);
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/*
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* pid_flash_load_schedule() — read gain schedule from flash.
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* Returns true and fills out_entries[0..n-1] and *out_n if magic is valid.
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* Returns false if no valid schedule stored.
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*/
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bool pid_flash_load_schedule(pid_sched_entry_t *out_entries, uint8_t *out_n);
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/*
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* pid_flash_save_all() — erase sector 7 once and atomically write both:
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* - pid_sched_flash_t at PID_SCHED_FLASH_ADDR (0x0807FF40)
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* - pid_flash_t at PID_FLASH_STORE_ADDR (0x0807FFC0)
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* Must not be called while armed. Returns true on success.
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*/
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bool pid_flash_save_all(float kp_single, float ki_single, float kd_single,
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const pid_sched_entry_t *entries, uint8_t num_bands);
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#endif /* PID_FLASH_H */
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