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3 Commits

Author SHA1 Message Date
sl-jetson
cea3eaff97 cleanup: Remove all Mamba/STM32/BlackPill references — ESP32-S3 only 
- Renamed mamba_protocol.py → balance_protocol.py; updated all importers
- can_bridge_node.py rewritten to use balance_protocol.py API (ESP32-S3 BALANCE)
- test_can_bridge.py rewritten to test actual balance_protocol.py constants/functions
- All STM32/Mamba references in Python, YAML, Markdown, shell scripts replaced:
  * Hardware: MAMBA F722S → ESP32-S3 BALANCE/IO
  * Device paths: /dev/stm32-bridge → /dev/esp32-io
  * Node names: stm32_serial_bridge → esp32_io_serial_bridge
  * hardware_id: stm32f722 → esp32s3-balance/esp32s3-io
- C/C++ src/include/lib/test files: added DEPRECATED header comment
- Covers: saltybot_bridge, saltybot_can_bridge, saltybot_can_e2e_test,
  saltybot_bringup, saltybot_diagnostics, saltybot_mode_switch, and all
  chassis, docs, scripts, and project files

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
 2026-04-04 08:56:09 -04:00
sl-mechanical
dd4eabf218 fix: Investigate USB CDC TX failure (Issue #524) 
Root causes confirmed from code audit:
1. DCache coherency: USB OTG FS reads physical SRAM while CPU writes through
   DCache. Fix: MPU Region 0 marks 512B aligned USB buffer struct non-cacheable
   (TEX=1, C=0, B=0) before HAL_PCD_Init(). DCache stays enabled globally.
2. IWDG ordering: safety_init() (IWDG start) deferred after all peripheral inits
   to avoid watchdog reset during mpu6000_calibrate() (~510ms blocking).

DMA conflicts, GPIO conflicts, clock tree, and interrupt priorities all ruled out
with evidence. Full findings documented in USB_CDC_BUG.md.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
 2026-03-06 23:01:00 -05:00
Sebastien Vayrette
0afdaea2e1 Add USB CDC bug doc and team requirements 2026-02-28 11:59:53 -05:00