saltylab-firmware

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Author	SHA1	Message	Date
sl-firmware	fbfde24aba	feat: CRSF/ELRS RC integration — 16ch input with failsafe (#Phase2) Protocol choice: implemented from spec (CRSFforArduino needs Arduino framework; Betaflight extraction has deep scheduler dependencies). Protocol verified against Betaflight src/main/rx/crsf.c + CRSF spec. crsf.c: - UART4 PA0=TX/PA1=RX (GPIO_AF8_UART4), 420000 baud 8N1, oversampling×8 APB1=54MHz → BRR=0x101 → 418604 baud (0.33% error, within spec) - DMA1 Stream2 Channel4, circular 64-byte buffer, IDLE interrupt DMA half/complete callbacks drain buffer; IDLE fires at frame boundary - CRC8 DVB-S2 (polynomial 0xD5) validated on every frame - Parser state machine: SYNC(0xC8)→LEN→DATA with length sanity check - 11-bit channel unpack for all 16 channels from 22-byte payload - RC channels frame (0x16): unpacks 16ch, updates last_rx_ms + armed - Link stats frame (0x14): captures RSSI dBm, LQ%, SNR dB crsf.h: added rssi_dbm, link_quality, snr fields to CRSFState config.h: CRSF_ARM_THRESHOLD=1750, CRSF_STEER_MAX=400, CRSF_FAILSAFE_MS=300 main.c: - crsf_init() called after motor_driver_init() - RC failsafe: disarm if (now - last_rx_ms) > CRSF_FAILSAFE_MS, but only after RC was first seen (last_rx_ms != 0) — USB-only mode unaffected - RC arm: CH5 rising edge → safety_arm_start(); falling edge → disarm Same ARMING_HOLD_MS interlock as USB arm command - RC steer: CH1 → crsf_to_range() → ±CRSF_STEER_MAX → motor_driver steer - RSSI/LQ: appended to JSON when safety_rc_alive() ("rssi","lq" fields) ui/index.html: hidden RC RSSI row revealed on first packet with rssi/lq Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>	2026-02-28 21:54:58 -05:00
sl-firmware	81d76e4770	fix(usb): MPU non-cacheable region + IWDG ordering fix (bd-3ulu) Root cause 1 (IWDG reset loop): safety_init() was called before mpu6000_init() — IWDG 50ms timeout fires during ~510ms IMU init, causing infinite MCU reset. Moved safety_init() to after all peripheral inits (IMU, hoverboard, balance). Root cause 2 (DCache coherency): USB TX/RX buffers merged into a single 512B-aligned struct in usbd_cdc_if.c. MPU Region 0 configured non-cacheable (TEX=1, C=0, B=0) in usbd_conf.c USBD_LL_Init() before HAL_PCD_Init(). DCache stays ON globally — MPU handles coherency. Removed SCB_DisableDCache() from main.c (caused boot crash). Also: fix safety.c IWDG_RELOAD macro (float literals not valid in #if); add crsf.c stub so crsf_state links (UART not yet wired). Fixes issue #9. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>	2026-02-28 13:51:02 -05:00

Author

SHA1

Message

Date

sl-firmware

fbfde24aba

feat: CRSF/ELRS RC integration — 16ch input with failsafe (#Phase2)

Protocol choice: implemented from spec (CRSFforArduino needs Arduino
framework; Betaflight extraction has deep scheduler dependencies).
Protocol verified against Betaflight src/main/rx/crsf.c + CRSF spec.

crsf.c:
- UART4 PA0=TX/PA1=RX (GPIO_AF8_UART4), 420000 baud 8N1, oversampling×8
  APB1=54MHz → BRR=0x101 → 418604 baud (0.33% error, within spec)
- DMA1 Stream2 Channel4, circular 64-byte buffer, IDLE interrupt
  DMA half/complete callbacks drain buffer; IDLE fires at frame boundary
- CRC8 DVB-S2 (polynomial 0xD5) validated on every frame
- Parser state machine: SYNC(0xC8)→LEN→DATA with length sanity check
- 11-bit channel unpack for all 16 channels from 22-byte payload
- RC channels frame (0x16): unpacks 16ch, updates last_rx_ms + armed
- Link stats frame (0x14): captures RSSI dBm, LQ%, SNR dB

crsf.h: added rssi_dbm, link_quality, snr fields to CRSFState

config.h: CRSF_ARM_THRESHOLD=1750, CRSF_STEER_MAX=400, CRSF_FAILSAFE_MS=300

main.c:
- crsf_init() called after motor_driver_init()
- RC failsafe: disarm if (now - last_rx_ms) > CRSF_FAILSAFE_MS, but only
  after RC was first seen (last_rx_ms != 0) — USB-only mode unaffected
- RC arm: CH5 rising edge → safety_arm_start(); falling edge → disarm
  Same ARMING_HOLD_MS interlock as USB arm command
- RC steer: CH1 → crsf_to_range() → ±CRSF_STEER_MAX → motor_driver steer
- RSSI/LQ: appended to JSON when safety_rc_alive() ("rssi","lq" fields)

ui/index.html: hidden RC RSSI row revealed on first packet with rssi/lq

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

2026-02-28 21:54:58 -05:00

sl-firmware

81d76e4770

fix(usb): MPU non-cacheable region + IWDG ordering fix (bd-3ulu)

Root cause 1 (IWDG reset loop): safety_init() was called before
mpu6000_init() — IWDG 50ms timeout fires during ~510ms IMU init,
causing infinite MCU reset. Moved safety_init() to after all
peripheral inits (IMU, hoverboard, balance).

Root cause 2 (DCache coherency): USB TX/RX buffers merged into a
single 512B-aligned struct in usbd_cdc_if.c. MPU Region 0 configured
non-cacheable (TEX=1, C=0, B=0) in usbd_conf.c USBD_LL_Init() before
HAL_PCD_Init(). DCache stays ON globally — MPU handles coherency.
Removed SCB_DisableDCache() from main.c (caused boot crash).

Also: fix safety.c IWDG_RELOAD macro (float literals not valid in
#if); add crsf.c stub so crsf_state links (UART not yet wired).

Fixes issue #9.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

2026-02-28 13:51:02 -05:00

2 Commits