Previous config had VESC_CAN_TX_GPIO=2 and DISP_BL_GPIO=2 — same pin,
making CAN permanently non-functional. Correct hardware layout (verified in
motor-test-firmware commit 8e66430): SN65HVD230 is on GPIO15/16, display
backlight on GPIO40, display reset on GPIO12.
Also adds IO_UART_TX/RX (GPIO17/18) for future ESP32 IO inter-board link.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
gc9a01.c and gc9a01.h were never committed to main despite ota_display.c
depending on their display_fill_rect/draw_string/draw_arc functions.
Also:
- CMakeLists.txt: add gc9a01.c to SRCS
- config.h: restore DISP_* GPIO defs (DC=8 CS=9 SCK=10 MOSI=11 RST=14 BL=2)
for Waveshare ESP32-S3-Touch-LCD-1.28
- ota_display.c: fix snprintf buffer too small (verline[32]→[48]) which
GCC 13.2.0 rejects as -Werror=format-truncation
Confirmed builds clean and boots on bd-66hx hardware (mbpi5 /dev/ttyACM0).
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Platform is no longer a self-balancing bot. Remove:
- TILT_CUTOFF_DEG (±25° tilt cutoff constant, was unused in ESP32-S3)
- BAL_TILT_FAULT state from bal_state_t enum (no code path generates it)
ESTOP and heartbeat watchdog are unchanged.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Replaces Orin↔ESP32-S3 BALANCE CAN comms (0x300-0x303 / 0x400-0x401)
with binary serial framing over CH343 USB-CDC at 460800 baud.
Protocol matches bd-wim1 (sl-perception) exactly:
Frame: [0xAA][LEN][TYPE][PAYLOAD][CRC8-SMBUS]
CRC covers LEN+TYPE+PAYLOAD, big-endian multi-byte fields.
Commands (Orin→ESP32): HEARTBEAT/DRIVE/ESTOP/ARM/PID
Telemetry (ESP32→Orin): TELEM_STATUS, TELEM_VESC_LEFT (ID 56),
TELEM_VESC_RIGHT (ID 68), ACK/NACK
VESC CAN TWAI kept for motor control; drive commands from Orin
forwarded to VESCs via SET_RPM. Hardware note: SN65HVD230
rewired from IO43/44 to IO2/IO1 to free IO43/44 for CH343.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
