saltylab-firmware

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Author	SHA1	Message	Date
sl-controls	64de6667b6	feat: PID gain scheduling for speed-dependent balance (Issue #550 ) Implements a speed-dependent PID gain scheduler that interpolates Kp/Ki/Kd across a configurable table of velocity breakpoints, replacing the fixed single-gain PID used previously. Changes: - include/pid_flash.h: add pid_sched_entry_t (16-byte entry), pid_sched_flash_t (128-byte record at 0x0807FF40), pid_flash_load_schedule(), pid_flash_save_all() (atomic single-sector erase for both schedule and single-PID records) - src/pid_flash.c: implement load_schedule and save_all; single erase covers both records at 0x0807FF40 (schedule) and 0x0807FFC0 (single PID) - include/pid_schedule.h: API header -- init, get_gains, apply, set/get table, flash_save, active_band_idx, get_default_table - src/pid_schedule.c: linear interpolation between sorted speed-band entries; integrator reset on band transition; default 3-band table (0/0.3/0.8 m/s) - include/jlink.h: add SCHED_GET (0x0C), SCHED_SET (0x0D), SCHED_SAVE (0x0E) commands; TLM_SCHED (0x85); jlink_tlm_sched_t; JLinkSchedSetBuf; sched_get_req, sched_save_req fields in JLinkState; include pid_flash.h - src/jlink.c: dispatch SCHED_GET/SET/SAVE; implement jlink_send_sched_telemetry, jlink_get_sched_set; add JLinkSchedSetBuf static buffer - test/test_pid_schedule.c: 48 unit tests -- all passing (gcc host build) Flash layout (sector 7): 0x0807FF40 pid_sched_flash_t (128 bytes) -- schedule 0x0807FFC0 pid_flash_t ( 64 bytes) -- single PID (existing) Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>	2026-03-14 10:41:34 -04:00
sl-firmware	19a30a1c4f	feat: PID auto-tune for balance mode (Issue #531 ) Implement Ziegler-Nichols relay feedback auto-tuning with flash persistence: Firmware (STM32F722): - pid_flash.c/h: erase+write Kp/Ki/Kd to flash sector 7 (0x0807FFC0), magic-validated; load on boot to restore saved tune - jlink.h: add JLINK_CMD_PID_SAVE (0x0A) and JLINK_TLM_PID_RESULT (0x83) with jlink_tlm_pid_result_t struct and pid_save_req flag in JLinkState - jlink.c: dispatch JLINK_CMD_PID_SAVE -> pid_save_req; add jlink_send_pid_result() to confirm flash write outcome over USART1 - main.c: load saved PID from flash after balance_init(); handle pid_save_req in main loop (disarmed-only, erase stalls CPU ~1s) Jetson ROS2 (saltybot_pid_autotune): - pid_autotune_node.py: add Ki to Ziegler-Nichols formula (ZN PID: Kp=0.6Ku, Ki=1.2Ku/Tu, Kd=0.075KuTu); add JLink serial client that sends JLINK_CMD_PID_SET + JLINK_CMD_PID_SAVE after tuning completes - autotune_config.yaml: add jlink_serial_port and jlink_baud_rate params Trigger: ros2 service call /saltybot/autotune_pid std_srvs/srv/Trigger Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>	2026-03-07 09:56:19 -05:00

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sl-controls

64de6667b6

feat: PID gain scheduling for speed-dependent balance (Issue #550 )

Implements a speed-dependent PID gain scheduler that interpolates Kp/Ki/Kd
across a configurable table of velocity breakpoints, replacing the fixed
single-gain PID used previously.

Changes:
- include/pid_flash.h: add pid_sched_entry_t (16-byte entry), pid_sched_flash_t
  (128-byte record at 0x0807FF40), pid_flash_load_schedule(), pid_flash_save_all()
  (atomic single-sector erase for both schedule and single-PID records)
- src/pid_flash.c: implement load_schedule and save_all; single erase covers
  both records at 0x0807FF40 (schedule) and 0x0807FFC0 (single PID)
- include/pid_schedule.h: API header -- init, get_gains, apply, set/get table,
  flash_save, active_band_idx, get_default_table
- src/pid_schedule.c: linear interpolation between sorted speed-band entries;
  integrator reset on band transition; default 3-band table (0/0.3/0.8 m/s)
- include/jlink.h: add SCHED_GET (0x0C), SCHED_SET (0x0D), SCHED_SAVE (0x0E)
  commands; TLM_SCHED (0x85); jlink_tlm_sched_t; JLinkSchedSetBuf;
  sched_get_req, sched_save_req fields in JLinkState; include pid_flash.h
- src/jlink.c: dispatch SCHED_GET/SET/SAVE; implement jlink_send_sched_telemetry,
  jlink_get_sched_set; add JLinkSchedSetBuf static buffer
- test/test_pid_schedule.c: 48 unit tests -- all passing (gcc host build)

Flash layout (sector 7):
  0x0807FF40  pid_sched_flash_t (128 bytes) -- schedule
  0x0807FFC0  pid_flash_t       ( 64 bytes) -- single PID (existing)

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

2026-03-14 10:41:34 -04:00

sl-firmware

19a30a1c4f

feat: PID auto-tune for balance mode (Issue #531 )

Implement Ziegler-Nichols relay feedback auto-tuning with flash persistence:

Firmware (STM32F722):
- pid_flash.c/h: erase+write Kp/Ki/Kd to flash sector 7 (0x0807FFC0),
  magic-validated; load on boot to restore saved tune
- jlink.h: add JLINK_CMD_PID_SAVE (0x0A) and JLINK_TLM_PID_RESULT (0x83)
  with jlink_tlm_pid_result_t struct and pid_save_req flag in JLinkState
- jlink.c: dispatch JLINK_CMD_PID_SAVE -> pid_save_req; add
  jlink_send_pid_result() to confirm flash write outcome over USART1
- main.c: load saved PID from flash after balance_init(); handle
  pid_save_req in main loop (disarmed-only, erase stalls CPU ~1s)

Jetson ROS2 (saltybot_pid_autotune):
- pid_autotune_node.py: add Ki to Ziegler-Nichols formula (ZN PID:
  Kp=0.6Ku, Ki=1.2Ku/Tu, Kd=0.075KuTu); add JLink serial client that
  sends JLINK_CMD_PID_SET + JLINK_CMD_PID_SAVE after tuning completes
- autotune_config.yaml: add jlink_serial_port and jlink_baud_rate params

Trigger: ros2 service call /saltybot/autotune_pid std_srvs/srv/Trigger

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

2026-03-07 09:56:19 -05:00

2 Commits