3 Commits

Author	SHA1	Message	Date
sl-webui	28c934deff	feat(arch): migrate all STM32/Mamba/BlackPill refs to ESP32 BALANCE/IO + fix roslib@1.4.0 ... Architecture change (2026-04-03): Mamba F722S (STM32F722) and BlackPill replaced by ESP32 BALANCE (PID loop) and ESP32 IO (motors/sensors/comms). - Update CLAUDE.md, docs, chassis BOM/ASSEMBLY, pinout, power-budget, wiring-diagram, TEAM.md, AUTONOMOUS_ARMING.md, docker-compose - Update all ROS2 package comments, config labels, launch args (stm32_port→esp32_port, /dev/stm32-bridge→/dev/esp32-bridge) - Update WebUI: stm32Mode→esp32Mode, stm32Version→esp32Version, "STM32 State/Mode" labels → "ESP32 State/Mode" (ControlMode, SettingsPanel) - Add TODO(esp32-migration) markers on stm32_protocol.py and mamba_protocol.py binary frame layouts — pending ESP32 protocol spec from max - Fix roslib CDN 1.3.0→1.4.0 in all 11 HTML panels (fixes ROS2 Humble rosbridge "Received a message without an op" incompatibility) Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>	2026-04-03 23:09:10 -04:00
sl-mechanical	dd4eabf218	fix: Investigate USB CDC TX failure (Issue #524) ... Root causes confirmed from code audit: 1. DCache coherency: USB OTG FS reads physical SRAM while CPU writes through DCache. Fix: MPU Region 0 marks 512B aligned USB buffer struct non-cacheable (TEX=1, C=0, B=0) before HAL_PCD_Init(). DCache stays enabled globally. 2. IWDG ordering: safety_init() (IWDG start) deferred after all peripheral inits to avoid watchdog reset during mpu6000_calibrate() (~510ms blocking). DMA conflicts, GPIO conflicts, clock tree, and interrupt priorities all ruled out with evidence. Full findings documented in USB_CDC_BUG.md. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>	2026-03-06 23:01:00 -05:00
Sebastien Vayrette	0afdaea2e1	Add USB CDC bug doc and team requirements	2026-02-28 11:59:53 -05:00