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fix: correct GPIO pins in config.h — CAN on 15/16, display BL/RST on 40/12

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Previous config had VESC_CAN_TX_GPIO=2 and DISP_BL_GPIO=2 — same pin,
making CAN permanently non-functional. Correct hardware layout (verified in
motor-test-firmware commit 8e66430): SN65HVD230 is on GPIO15/16, display
backlight on GPIO40, display reset on GPIO12.

Also adds IO_UART_TX/RX (GPIO17/18) for future ESP32 IO inter-board link.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
This commit is contained in:
sl-jetson 2026-04-20 19:09:20 -04:00
parent a6e7c4a550
commit 7a4b278704
1 changed files with 19 additions and 15 deletions
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34
esp32s3/balance/main/config.h
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@ -1,40 +1,44 @@
#pragma once #pragma once
/* ── ESP32-S3 BALANCE board — bd-66hx pin/config definitions ─────────────── /* ── ESP32-S3 BALANCE board — Waveshare ESP32-S3-Touch-LCD-1.28 pinout ─────
* *
* Hardware change from pre-bd-66hx design: * Orin comms: CH343 USB-to-serial on UART0 (GPIO43/44) → /dev/ttyACM0 on Orin
* Previously: IO43/IO44 = CAN SN65HVD230 (shared Orin+VESC bus via CANable2) * VESC CAN: SN65HVD230 transceiver on GPIO15 (TX) / GPIO16 (RX)
* After bd-66hx: IO43/IO44 = CH343 UART0 (Orin serial comms) * Display: GC9A01 on SPI2 — BL=GPIO40, RST=GPIO12
* IO2/IO1 = CAN SN65HVD230 rewired (VESC-only bus)
* *
* The SN65HVD230 transceiver physical wiring must be updated from IO43/44 * GPIO2 is NOT used for CAN — it is free. Earlier versions had an erroneous
* to IO2/IO1 when deploying this firmware. See docs/SAUL-TEE-SYSTEM-REFERENCE.md. * conflict between DISP_BL (GPIO2) and VESC_CAN_TX (GPIO2); corrected here
* to match motor-test-firmware verified hardware layout (commit 8e66430).
*/ */
/* ── Orin serial (CH343 USB-to-UART, 1a86:55d3 on Orin side) ── */ /* ── Orin serial (CH343 USB-to-UART, 1a86:55d3 on Orin side) ── */
#define ORIN_UART_PORT UART_NUM_0 #define ORIN_UART_PORT UART_NUM_0
#define ORIN_UART_BAUD 460800 #define ORIN_UART_BAUD 460800
#define ORIN_UART_TX_GPIO 43 /* ESP32→CH343 RXD */ #define ORIN_UART_TX_GPIO 43 /* ESP32 UART0 TX → CH343 RXD */
#define ORIN_UART_RX_GPIO 44 /* CH343 TXD→ESP32 */ #define ORIN_UART_RX_GPIO 44 /* CH343 TXD → ESP32 UART0 RX */
#define ORIN_UART_RX_BUF 1024 #define ORIN_UART_RX_BUF 1024
#define ORIN_TX_QUEUE_DEPTH 16 #define ORIN_TX_QUEUE_DEPTH 16
/* ── VESC CAN TWAI (SN65HVD230 transceiver, rewired for bd-66hx) ── */ /* ── Inter-board UART (ESP32 BALANCE ↔ ESP32 IO) ── */
#define VESC_CAN_TX_GPIO 2 /* ESP32 TWAI TX → SN65HVD230 TXD */ #define IO_UART_TX_GPIO 17
#define VESC_CAN_RX_GPIO 1 /* SN65HVD230 RXD → ESP32 TWAI RX */ #define IO_UART_RX_GPIO 18
/* ── VESC CAN TWAI (SN65HVD230 on Waveshare header GPIO15/16) ── */
#define VESC_CAN_TX_GPIO 15 /* ESP32 TWAI TX → SN65HVD230 TXD */
#define VESC_CAN_RX_GPIO 16 /* SN65HVD230 RXD → ESP32 TWAI RX */
#define VESC_CAN_RX_QUEUE 32 #define VESC_CAN_RX_QUEUE 32
/* VESC node IDs — matched to bd-wim1 TELEM_VESC_LEFT/RIGHT mapping */ /* VESC node IDs — matched to bd-wim1 TELEM_VESC_LEFT/RIGHT mapping */
#define VESC_ID_A 56u /* TELEM_VESC_LEFT (0x81) */ #define VESC_ID_A 56u /* TELEM_VESC_LEFT (0x81) */
#define VESC_ID_B 68u /* TELEM_VESC_RIGHT (0x82) */ #define VESC_ID_B 68u /* TELEM_VESC_RIGHT (0x82) */
/* ── GC9A01 240×240 round display (Waveshare ESP32-S3-Touch-LCD-1.28) ── */ /* ── GC9A01 240×240 round display (Waveshare ESP32-S3-Touch-LCD-1.28, SPI2) ── */
#define DISP_DC_GPIO 8 #define DISP_DC_GPIO 8
#define DISP_CS_GPIO 9 #define DISP_CS_GPIO 9
#define DISP_SCK_GPIO 10 #define DISP_SCK_GPIO 10
#define DISP_MOSI_GPIO 11 #define DISP_MOSI_GPIO 11
#define DISP_RST_GPIO 14 #define DISP_RST_GPIO 12
#define DISP_BL_GPIO 2 #define DISP_BL_GPIO 40
/* ── Safety / timing ── */ /* ── Safety / timing ── */
#define HB_TIMEOUT_MS 500u /* heartbeat watchdog: disarm if exceeded */ #define HB_TIMEOUT_MS 500u /* heartbeat watchdog: disarm if exceeded */