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Netlist-first KiCad-import package for the single carrier PCB (ESP32-WROOM-32E, SINK/BROADCASTER assembly variants): - hardware/carrier/resound-carrier.net : KiCad s-expr netlist, 44 components / 40 nets, real library footprints (RF_Module:ESP32-WROOM-32, 2x13 stacking header, 0402 passives, SOT-23 auto-reset, JST-SH HUD conn). Parens balanced. - hardware/carrier/BOM.csv : 44 parts (ref/value/footprint/MPN/DNP/notes). - hardware/carrier/LAYOUT.md : 45x45 4-layer stackup, 15mm antenna keep-out, placement, JLCPCB DRC, SINK-vs-BROADCASTER variant + address-strap table. - hardware/carrier/README.md : KiCad import steps + caveats. Agent decisions flagged for EE: LED moved off the GPIO13 strap to LED_DAT=GPIO21 / LED_CLK=GPIO4; verify WROOM footprint pad numbering; UART2 is connector-only this rev. Deliverable is import-ready netlist+BOM+spec, not a finished .kicad_pcb. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
85 lines
5.3 KiB
Markdown
85 lines
5.3 KiB
Markdown
# Resound Small Build — Carrier PCB (KiCad bootstrap)
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A netlist-first hardware bootstrap for the **Resound** carrier PCB: one 45 x 45 mm
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4-layer board built around an **ESP32-WROOM-32E**, with a 26-pin stacking bus, that
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ships in two assembly variants — **SINK** and **BROADCASTER** — from the same layout.
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## What's here
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| File | Purpose |
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|------|---------|
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| `resound-carrier.net` | KiCad S-expression netlist: every component (ref/value/**real KiCad footprint**) and every net with pin connections. The importable artifact. |
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| `BOM.csv` | Bill of materials: Ref, Qty, Value, Footprint, MPN/JLCPCB, DNP, Notes. |
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| `LAYOUT.md` | Board outline, 4-layer stackup, antenna keep-out, placement plan, mounting holes, JLCPCB design rules, and the SINK vs BROADCASTER variant table. |
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| `README.md` | This file. |
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## Honest scope
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A text agent cannot emit a guaranteed-openable `.kicad_pcb` with real geometry. So the
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deliverable is a **complete, accurate, importable netlist + BOM + layout spec**. The
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schematic is **not yet drawn** — this is a netlist-first workflow. An engineer imports
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the netlist, lays out the board per `LAYOUT.md`, and (optionally) back-annotates a
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schematic afterwards.
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## How to import into KiCad (8.x)
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### Option A — straight into the PCB editor (fastest, matches netlist-first)
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1. New KiCad project. Open the **PCB Editor** (Pcbnew).
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2. **File -> Import -> Netlist...** Select `resound-carrier.net`.
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3. KiCad places all footprints (it resolves the library footprint names like
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`RF_Module:ESP32-WROOM-32`, `Connector_PinHeader_2.54mm:PinHeader_2x13_P2.54mm_Vertical`,
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`Resistor_SMD:R_0402_1005Metric`, `Package_TO_SOT_SMD:SOT-23`, etc. from the standard
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KiCad footprint libraries — make sure those libs are installed/enabled).
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4. Build the board outline on **Edge.Cuts** (45x45, rounded corners) and lay out per
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`LAYOUT.md`. Add the antenna keep-out zones, GND/PWR plane pours, and mounting holes.
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5. Run **DRC** with JLCPCB rules from `LAYOUT.md` section 6.
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### Option B — schematic-first (if you prefer drawing the schematic)
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1. Use the netlist as the connectivity spec and draw the schematic in Eeschema, matching
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refs/nets exactly, then **Update PCB from Schematic** (F8). The provided `.net` is the
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single source of truth for which pin connects to which net.
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> Note: the `.net` uses KiCad's S-expression `(export ...)` netlist format with
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> `(comp ...)` + `(net ...)` sections and per-component `(footprint ...)`. This is what
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> "Import Netlist" consumes. The `(libparts)`/`(libraries)` blocks are intentionally empty
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> (footprints are assigned directly on each component, which is sufficient for PCB import).
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## ESP32-WROOM-32E pad mapping used
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The netlist references U1 by the standard KiCad `RF_Module:ESP32-WROOM-32` footprint pad
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numbers 1..38 (+ EP on pad 38). Key assignments:
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- GND = pads 1, 15, 38(EP) | 3V3 = pad 2 | EN = pad 3
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- I2C: SDA=GPIO32 (pad 8), SCL=GPIO33 (pad 9)
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- I2S SINK: BCK=GPIO5 (pad 29), WS=GPIO25 (pad 10), DATA=GPIO23 (pad 37)
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- I2S BCAST: BCK=GPIO19 (pad 31), WS=GPIO18 (pad 30), DATA=GPIO22 (pad 36)
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- ADDR: GPIO13 (pad 16), GPIO14 (pad 13), GPIO27 (pad 12), GPIO26 (pad 11)
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- UART bus: TX=GPIO17 (pad 28), RX=GPIO16 (pad 27)
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- LED: DAT=GPIO21 (pad 33), CLK=GPIO4 (pad 26) *(reassigned — see caveats)*
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- Prog UART0: RX/IO3=GPIO3 (pad 34), TX/IO1=GPIO1 (pad 35), IO0=pad 25
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**Verify this pad mapping against the exact footprint variant you load** before committing
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copper, since some WROOM footprint variants renumber pads.
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## Known caveats / open items for the EE
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1. **LED pin reuse (RESOLVE THIS).** The original spec note put the APA102 LED DATA on
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GPIO13, but GPIO13 is already an **address strap** (ADDR0). To avoid the conflict the
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netlist reassigns LED to spare pins: **LED_DAT = GPIO21, LED_CLK = GPIO4**. Confirm
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these spares are truly free for your firmware and that GPIO4/GPIO21 have no strapping or
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boot side-effects in your build. Adjust if needed — flagged intentionally.
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2. **Antenna coupling across the stack.** Boards stack vertically; the WROOM antenna of a
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lower board sits near the copper/components of the board above. Enforce the 15 mm
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all-layer keep-out (LAYOUT.md §4) and consider stack spacing / antenna orientation so
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the antenna of any board does not sit under metal of the neighbor.
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3. **Verify HUD SH1.0 pin order.** J3 is keyed/genderable; confirm pin 1 of the chosen
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SH1.0 connector and the HUD cable match the `1=+5V 2=GND 3=SDA 4=SCL 5=SPARE 6=NC`
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order before fab. Easy to mirror.
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4. **UART2 bus pins (J1 19/20)** are connector pass-through only on this rev — no MCU tap
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is routed (the ESP32 second hardware UART pins are not broken out here). If a board
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needs to drive UART2, the EE must route MCU spares to those connector pins.
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5. **Auto-reset cross-bias.** The DTR/RTS auto-reset/boot circuit follows the NodeMCU
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2-transistor pattern; the base-resistor cross-bias nets (R8_BIAS->RTS, R9_BIAS->DTR)
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prevent EN+IO0 asserting simultaneously. Sanity-check against your USB-serial adapter's
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DTR/RTS polarity.
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6. **I2S series terminators R1/R2/R3** are DNP by default (direct connection). Populate
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33R only if I2S signals ring across the stack.
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## Variants in one line
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SINK = I2S jumpers JP1/JP2/JP3 + I2C pull-ups R4/R5 populated. BROADCASTER = I2S jumpers
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JP4/JP5/JP6, pull-ups DNP. Address straps set per board. Full table in `LAYOUT.md` §7.
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