Netlist-first KiCad-import package for the single carrier PCB (ESP32-WROOM-32E, SINK/BROADCASTER assembly variants): - hardware/carrier/resound-carrier.net : KiCad s-expr netlist, 44 components / 40 nets, real library footprints (RF_Module:ESP32-WROOM-32, 2x13 stacking header, 0402 passives, SOT-23 auto-reset, JST-SH HUD conn). Parens balanced. - hardware/carrier/BOM.csv : 44 parts (ref/value/footprint/MPN/DNP/notes). - hardware/carrier/LAYOUT.md : 45x45 4-layer stackup, 15mm antenna keep-out, placement, JLCPCB DRC, SINK-vs-BROADCASTER variant + address-strap table. - hardware/carrier/README.md : KiCad import steps + caveats. Agent decisions flagged for EE: LED moved off the GPIO13 strap to LED_DAT=GPIO21 / LED_CLK=GPIO4; verify WROOM footprint pad numbering; UART2 is connector-only this rev. Deliverable is import-ready netlist+BOM+spec, not a finished .kicad_pcb. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
5.3 KiB
Resound Small Build — Carrier PCB (KiCad bootstrap)
A netlist-first hardware bootstrap for the Resound carrier PCB: one 45 x 45 mm 4-layer board built around an ESP32-WROOM-32E, with a 26-pin stacking bus, that ships in two assembly variants — SINK and BROADCASTER — from the same layout.
What's here
| File | Purpose |
|---|---|
resound-carrier.net |
KiCad S-expression netlist: every component (ref/value/real KiCad footprint) and every net with pin connections. The importable artifact. |
BOM.csv |
Bill of materials: Ref, Qty, Value, Footprint, MPN/JLCPCB, DNP, Notes. |
LAYOUT.md |
Board outline, 4-layer stackup, antenna keep-out, placement plan, mounting holes, JLCPCB design rules, and the SINK vs BROADCASTER variant table. |
README.md |
This file. |
Honest scope
A text agent cannot emit a guaranteed-openable .kicad_pcb with real geometry. So the
deliverable is a complete, accurate, importable netlist + BOM + layout spec. The
schematic is not yet drawn — this is a netlist-first workflow. An engineer imports
the netlist, lays out the board per LAYOUT.md, and (optionally) back-annotates a
schematic afterwards.
How to import into KiCad (8.x)
Option A — straight into the PCB editor (fastest, matches netlist-first)
- New KiCad project. Open the PCB Editor (Pcbnew).
- File -> Import -> Netlist... Select
resound-carrier.net. - KiCad places all footprints (it resolves the library footprint names like
RF_Module:ESP32-WROOM-32,Connector_PinHeader_2.54mm:PinHeader_2x13_P2.54mm_Vertical,Resistor_SMD:R_0402_1005Metric,Package_TO_SOT_SMD:SOT-23, etc. from the standard KiCad footprint libraries — make sure those libs are installed/enabled). - Build the board outline on Edge.Cuts (45x45, rounded corners) and lay out per
LAYOUT.md. Add the antenna keep-out zones, GND/PWR plane pours, and mounting holes. - Run DRC with JLCPCB rules from
LAYOUT.mdsection 6.
Option B — schematic-first (if you prefer drawing the schematic)
- Use the netlist as the connectivity spec and draw the schematic in Eeschema, matching
refs/nets exactly, then Update PCB from Schematic (F8). The provided
.netis the single source of truth for which pin connects to which net.
Note: the
.netuses KiCad's S-expression(export ...)netlist format with(comp ...)+(net ...)sections and per-component(footprint ...). This is what "Import Netlist" consumes. The(libparts)/(libraries)blocks are intentionally empty (footprints are assigned directly on each component, which is sufficient for PCB import).
ESP32-WROOM-32E pad mapping used
The netlist references U1 by the standard KiCad RF_Module:ESP32-WROOM-32 footprint pad
numbers 1..38 (+ EP on pad 38). Key assignments:
- GND = pads 1, 15, 38(EP) | 3V3 = pad 2 | EN = pad 3
- I2C: SDA=GPIO32 (pad 8), SCL=GPIO33 (pad 9)
- I2S SINK: BCK=GPIO5 (pad 29), WS=GPIO25 (pad 10), DATA=GPIO23 (pad 37)
- I2S BCAST: BCK=GPIO19 (pad 31), WS=GPIO18 (pad 30), DATA=GPIO22 (pad 36)
- ADDR: GPIO13 (pad 16), GPIO14 (pad 13), GPIO27 (pad 12), GPIO26 (pad 11)
- UART bus: TX=GPIO17 (pad 28), RX=GPIO16 (pad 27)
- LED: DAT=GPIO21 (pad 33), CLK=GPIO4 (pad 26) (reassigned — see caveats)
- Prog UART0: RX/IO3=GPIO3 (pad 34), TX/IO1=GPIO1 (pad 35), IO0=pad 25 Verify this pad mapping against the exact footprint variant you load before committing copper, since some WROOM footprint variants renumber pads.
Known caveats / open items for the EE
- LED pin reuse (RESOLVE THIS). The original spec note put the APA102 LED DATA on GPIO13, but GPIO13 is already an address strap (ADDR0). To avoid the conflict the netlist reassigns LED to spare pins: LED_DAT = GPIO21, LED_CLK = GPIO4. Confirm these spares are truly free for your firmware and that GPIO4/GPIO21 have no strapping or boot side-effects in your build. Adjust if needed — flagged intentionally.
- Antenna coupling across the stack. Boards stack vertically; the WROOM antenna of a lower board sits near the copper/components of the board above. Enforce the 15 mm all-layer keep-out (LAYOUT.md §4) and consider stack spacing / antenna orientation so the antenna of any board does not sit under metal of the neighbor.
- Verify HUD SH1.0 pin order. J3 is keyed/genderable; confirm pin 1 of the chosen
SH1.0 connector and the HUD cable match the
1=+5V 2=GND 3=SDA 4=SCL 5=SPARE 6=NCorder before fab. Easy to mirror. - UART2 bus pins (J1 19/20) are connector pass-through only on this rev — no MCU tap is routed (the ESP32 second hardware UART pins are not broken out here). If a board needs to drive UART2, the EE must route MCU spares to those connector pins.
- Auto-reset cross-bias. The DTR/RTS auto-reset/boot circuit follows the NodeMCU 2-transistor pattern; the base-resistor cross-bias nets (R8_BIAS->RTS, R9_BIAS->DTR) prevent EN+IO0 asserting simultaneously. Sanity-check against your USB-serial adapter's DTR/RTS polarity.
- I2S series terminators R1/R2/R3 are DNP by default (direct connection). Populate 33R only if I2S signals ring across the stack.
Variants in one line
SINK = I2S jumpers JP1/JP2/JP3 + I2C pull-ups R4/R5 populated. BROADCASTER = I2S jumpers
JP4/JP5/JP6, pull-ups DNP. Address straps set per board. Full table in LAYOUT.md §7.