sl-firmware
fa75c442a7
Archive STM32 firmware to legacy/stm32/: - src/, include/, lib/USB_CDC/, platformio.ini, test stubs, flash_firmware.py - test/test_battery_adc.c, test_hw_button.c, test_pid_schedule.c, test_vesc_can.c, test_can_watchdog.c - USB_CDC_BUG.md Rename: stm32_protocol → esp32_protocol, mamba_protocol → balance_protocol, stm32_cmd_node → esp32_cmd_node, stm32_cmd_params → esp32_cmd_params, stm32_cmd.launch.py → esp32_cmd.launch.py, test_stm32_protocol → test_esp32_protocol, test_stm32_cmd_node → test_esp32_cmd_node Content cleanup across all files: - Mamba F722S → ESP32-S3 BALANCE - BlackPill → ESP32-S3 IO - STM32F722/F7xx → ESP32-S3 - stm32Mode/Version/Port → esp32Mode/Version/Port - STM32 State/Mode labels → ESP32 State/Mode - Jetson Nano → Jetson Orin Nano Super - /dev/stm32 → /dev/esp32 - stm32_bridge → esp32_bridge - STM32 HAL → ESP-IDF docs/SALTYLAB.md: - Update "Drone FC Details" to describe ESP32-S3 BALANCE board (Waveshare ESP32-S3 Touch LCD 1.28) - Replace verbose "Self-Balancing Control" STM32 section with brief note pointing to SAUL-TEE-SYSTEM-REFERENCE.md TEAM.md: Update Embedded Firmware Engineer role to ESP32-S3 / ESP-IDF No new functionality — cleanup only. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
#include "ota.h"
|
||
#include "stm32f7xx_hal.h"
|
||
|
||
/* ---- ota_enter_dfu() ---- */
|
||
bool ota_enter_dfu(bool is_armed)
|
||
{
|
||
if (is_armed) return false;
|
||
|
||
/* Enable backup domain access */
|
||
__HAL_RCC_PWR_CLK_ENABLE();
|
||
HAL_PWR_EnableBkUpAccess();
|
||
__HAL_RCC_RTC_ENABLE();
|
||
|
||
/*
|
||
* Write DFU magic to BKP15R.
|
||
* checkForBootloader() runs on next boot and jumps to the ST system
|
||
* bootloader at 0x1FF00000 when it finds this magic in BKP15R.
|
||
* BKP15R avoids the BNO055 calibration range (BKP0R–BKP6R).
|
||
*
|
||
* RTC->BKP0R through BKP31R are laid out consecutively in memory,
|
||
* so (&RTC->BKP0R)[OTA_DFU_BKP_IDX] reaches BKP15R.
|
||
*/
|
||
(&RTC->BKP0R)[OTA_DFU_BKP_IDX] = OTA_DFU_MAGIC;
|
||
|
||
__disable_irq();
|
||
NVIC_SystemReset();
|
||
|
||
return true; /* never reached */
|
||
}
|
||
|
||
/* ---- ota_fw_crc32() ---- */
|
||
uint32_t ota_fw_crc32(void)
|
||
{
|
||
/*
|
||
* STM32F7 hardware CRC unit:
|
||
* Polynomial : 0x04C11DB7 (CRC-32/MPEG-2)
|
||
* Initial : 0xFFFFFFFF (CRC_INIT register default)
|
||
* Width : 32 bits
|
||
* Reflection : none
|
||
*
|
||
* The unit processes one 32-bit word at a time. Feeding the full
|
||
* 512 KB flash (128 K words) takes ~0.5 ms at 216 MHz.
|
||
*/
|
||
__HAL_RCC_CRC_CLK_ENABLE();
|
||
|
||
/* Reset CRC state; keep default 32-bit polynomial and no reversal */
|
||
CRC->CR = CRC_CR_RESET;
|
||
|
||
const uint32_t *p = (const uint32_t *)OTA_FLASH_BASE;
|
||
uint32_t words = OTA_FLASH_SIZE / 4u;
|
||
|
||
while (words--) {
|
||
CRC->DR = *p++;
|
||
}
|
||
|
||
return CRC->DR;
|
||
}
|