Sebastien Vayrette affaefea3a fix: Revert to 40MHz SPI, remove early fill (was causing boot loop) ...

80MHz SPI + immediate display_fill_rect in init caused RTC_SW_CPU_RST
boot loop. Revert to 40MHz and let hud_task handle first draw.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-04-20 13:46:42 -04:00

..

main

fix: Revert to 40MHz SPI, remove early fill (was causing boot loop)

2026-04-20 13:46:42 -04:00

CMakeLists.txt

feat: add UART/USB serial protocol for Orin comms, proxy VESC CAN (bd-66hx)

2026-04-17 22:09:12 -04:00

partitions.csv

feat: partition tables + OTA setup for Balance and IO boards (bd-3gwo)

2026-04-17 23:10:51 -04:00

sdkconfig.defaults

feat: Motor test firmware — orin_serial, sdkconfig, CMakeLists cleanup, tilt config

2026-04-20 10:43:08 -04:00