sl-firmware
972db16635
Balance side (uart_ota.c): downloads io-firmware.bin from Gitea to RAM, computes SHA256, then streams to IO over UART1 (GPIO17/18, 460800 baud) as OTA_BEGIN/OTA_DATA/OTA_END frames with CRC8 + per-chunk ACK/retry (×3). IO side (uart_ota_recv.c): receives frames, writes to inactive OTA partition via esp_ota_write, verifies SHA256 on OTA_END, sets boot partition, reboots. IO board main.c + CMakeLists.txt scaffold included. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
211 lines
6.5 KiB
C
211 lines
6.5 KiB
C
/* uart_ota_recv.c — IO board OTA receiver (bd-21hv)
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*
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* Listens on UART0 for OTA frames from Balance board.
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* Writes incoming chunks to the inactive OTA partition, verifies SHA256,
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* then reboots into new firmware.
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*/
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#include "uart_ota_recv.h"
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#include "config.h"
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#include "esp_log.h"
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#include "esp_ota_ops.h"
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#include "driver/uart.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "mbedtls/sha256.h"
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#include <string.h>
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static const char *TAG = "io_ota";
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volatile io_ota_state_t g_io_ota_state = IO_OTA_IDLE;
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volatile uint8_t g_io_ota_progress = 0;
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/* Frame type bytes (same as uart_ota.h sender side) */
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#define OTA_BEGIN 0xC0u
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#define OTA_DATA 0xC1u
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#define OTA_END 0xC2u
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#define OTA_ABORT 0xC3u
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#define OTA_ACK 0xC4u
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#define OTA_NACK 0xC5u
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#define CHUNK_MAX 1024
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static uint8_t crc8(const uint8_t *d, uint16_t len)
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{
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uint8_t crc = 0;
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for (uint16_t i = 0; i < len; i++) {
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crc ^= d[i];
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for (uint8_t b = 0; b < 8; b++)
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crc = (crc & 0x80u) ? (uint8_t)((crc << 1u) ^ 0x07u) : (uint8_t)(crc << 1u);
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}
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return crc;
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}
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static void send_ack(uint16_t seq)
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{
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uint8_t frame[6];
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frame[0] = OTA_ACK;
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frame[1] = (uint8_t)(seq >> 8u);
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frame[2] = (uint8_t)(seq);
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frame[3] = 0; frame[4] = 0; /* LEN=0 */
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uint8_t crc = crc8(frame, 5);
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frame[5] = crc;
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uart_write_bytes(IO_UART_PORT, (char *)frame, 6);
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}
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static void send_nack(uint16_t seq, uint8_t err)
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{
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uint8_t frame[8];
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frame[0] = OTA_NACK;
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frame[1] = (uint8_t)(seq >> 8u);
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frame[2] = (uint8_t)(seq);
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frame[3] = 0; frame[4] = 1; /* LEN=1 */
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frame[5] = err;
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uint8_t crc = crc8(frame, 6);
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frame[6] = crc;
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uart_write_bytes(IO_UART_PORT, (char *)frame, 7);
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}
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/* Read exact n bytes with timeout */
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static bool uart_read_exact(uint8_t *buf, int n, int timeout_ms)
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{
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int got = 0;
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while (got < n && timeout_ms > 0) {
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int r = uart_read_bytes(IO_UART_PORT, buf + got, n - got,
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pdMS_TO_TICKS(50));
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if (r > 0) got += r;
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else timeout_ms -= 50;
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}
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return got == n;
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}
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static void ota_recv_task(void *arg)
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{
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esp_ota_handle_t handle = 0;
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const esp_partition_t *ota_part = esp_ota_get_next_update_partition(NULL);
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mbedtls_sha256_context sha;
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mbedtls_sha256_init(&sha);
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uint32_t expected_size = 0;
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uint8_t expected_digest[32] = {0};
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uint32_t received = 0;
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bool ota_started = false;
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static uint8_t payload[CHUNK_MAX];
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for (;;) {
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/* Read frame header: TYPE(1) + SEQ(2) + LEN(2) = 5 bytes */
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uint8_t hdr[5];
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if (!uart_read_exact(hdr, 5, 5000)) continue;
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uint8_t type = hdr[0];
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uint16_t seq = (uint16_t)((hdr[1] << 8u) | hdr[2]);
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uint16_t plen = (uint16_t)((hdr[3] << 8u) | hdr[4]);
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if (plen > CHUNK_MAX + 36) {
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ESP_LOGW(TAG, "oversized frame plen=%u", plen);
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continue;
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}
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/* Read payload + CRC */
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if (plen > 0 && !uart_read_exact(payload, plen, 2000)) continue;
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uint8_t crc_rx;
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if (!uart_read_exact(&crc_rx, 1, 500)) continue;
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/* Verify CRC over hdr+payload */
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uint8_t crc_buf[5 + CHUNK_MAX + 36];
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memcpy(crc_buf, hdr, 5);
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if (plen > 0) memcpy(crc_buf + 5, payload, plen);
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uint8_t expected_crc = crc8(crc_buf, (uint16_t)(5 + plen));
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if (crc_rx != expected_crc) {
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ESP_LOGW(TAG, "CRC fail seq=%u", seq);
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send_nack(seq, 0x01u); /* OTA_ERR_BAD_CRC */
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continue;
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}
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switch (type) {
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case OTA_BEGIN:
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if (plen < 36) { send_nack(seq, 0x03u); break; }
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expected_size = ((uint32_t)payload[0] << 24u) |
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((uint32_t)payload[1] << 16u) |
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((uint32_t)payload[2] << 8u) |
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(uint32_t)payload[3];
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memcpy(expected_digest, &payload[4], 32);
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if (!ota_part || esp_ota_begin(ota_part, OTA_WITH_SEQUENTIAL_WRITES,
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&handle) != ESP_OK) {
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send_nack(seq, 0x02u);
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break;
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}
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mbedtls_sha256_starts(&sha, 0);
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received = 0;
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ota_started = true;
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g_io_ota_state = IO_OTA_RECEIVING;
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g_io_ota_progress = 0;
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ESP_LOGI(TAG, "OTA begin: %lu bytes", (unsigned long)expected_size);
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send_ack(seq);
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break;
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case OTA_DATA:
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if (!ota_started) { send_nack(seq, 0x02u); break; }
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if (esp_ota_write(handle, payload, plen) != ESP_OK) {
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send_nack(seq, 0x02u);
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esp_ota_abort(handle);
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ota_started = false;
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g_io_ota_state = IO_OTA_FAILED;
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break;
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}
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mbedtls_sha256_update(&sha, payload, plen);
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received += plen;
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if (expected_size > 0)
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g_io_ota_progress = (uint8_t)((received * 100u) / expected_size);
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send_ack(seq);
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break;
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case OTA_END: {
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if (!ota_started) { send_nack(seq, 0x02u); break; }
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g_io_ota_state = IO_OTA_VERIFYING;
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uint8_t digest[32];
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mbedtls_sha256_finish(&sha, digest);
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if (memcmp(digest, expected_digest, 32) != 0) {
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ESP_LOGE(TAG, "SHA256 mismatch");
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esp_ota_abort(handle);
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send_nack(seq, 0x01u);
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g_io_ota_state = IO_OTA_FAILED;
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break;
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}
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if (esp_ota_end(handle) != ESP_OK ||
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esp_ota_set_boot_partition(ota_part) != ESP_OK) {
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send_nack(seq, 0x02u);
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g_io_ota_state = IO_OTA_FAILED;
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break;
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}
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g_io_ota_state = IO_OTA_REBOOTING;
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g_io_ota_progress = 100;
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ESP_LOGI(TAG, "OTA done — rebooting");
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send_ack(seq);
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vTaskDelay(pdMS_TO_TICKS(500));
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esp_restart();
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break;
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}
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case OTA_ABORT:
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if (ota_started) { esp_ota_abort(handle); ota_started = false; }
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g_io_ota_state = IO_OTA_IDLE;
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ESP_LOGW(TAG, "OTA aborted");
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break;
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default:
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break;
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}
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}
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}
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void uart_ota_recv_init(void)
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{
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/* UART0 already initialized for inter-board comms; just create the task */
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xTaskCreate(ota_recv_task, "io_ota_recv", 8192, NULL, 6, NULL);
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ESP_LOGI(TAG, "OTA receiver task started");
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}
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