sl-firmware
4beef8da03
- Add ota.h / ota.c: ota_enter_dfu() (armed guard, writes BKP15R, resets), ota_fw_crc32() using STM32F7 hardware CRC peripheral (CRC-32/MPEG-2, 512 KB) - Add JLINK_CMD_DFU_ENTER (0x06) and dfu_req flag to jlink.h / jlink.c - Handle dfu_req in main loop: calls ota_enter_dfu(is_armed) — no-op if armed - Update usbd_cdc_if.c: move DFU magic from BKP0R to BKP15R (OTA_DFU_BKP_IDX) resolving BKP register conflict with BNO055 calibration (BKP0R–6R, PR #150) - Add scripts/flash_firmware.py: CRC-32/MPEG-2 + ISO-HDLC verification, dfu-util flash, host-side backup/rollback, --trigger-dfu JLink serial path - Add test/test_ota.py: 42 tests passing (CRC-32/MPEG-2, CRC-16/XMODEM, DFU_ENTER frame structure, BKP register safety, flash constants) Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
261 lines
9.2 KiB
Python
261 lines
9.2 KiB
Python
"""
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test_ota.py — OTA firmware update utilities (Issue #124)
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Tests:
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- CRC-32/ISO-HDLC (crc32_file / binascii.crc32)
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- CRC-32/MPEG-2 (stm32_crc32 — matches STM32F7 hardware CRC unit)
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- CRC-16/XMODEM (_crc16_xmodem — JLink frame integrity)
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- DFU_ENTER frame (JLINK_CMD_DFU_ENTER = 0x06, no payload)
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- Safety constants (BKP index, flash region, magic value)
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"""
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import binascii
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import os
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import struct
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import sys
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import tempfile
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import pytest
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# Add scripts directory to path so we can import flash_firmware.py
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sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..', 'scripts'))
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from flash_firmware import (
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crc32_file,
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stm32_crc32,
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_crc16_xmodem,
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_build_jlink_frame,
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FLASH_BASE,
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FLASH_SIZE,
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DFU_VID,
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DFU_PID,
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)
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# ── CRC-32/ISO-HDLC (crc32_file) ──────────────────────────────────────────
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class TestCrc32File:
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def test_known_empty(self, tmp_path):
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"""binascii.crc32 of empty file = 0x00000000."""
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p = tmp_path / "empty.bin"
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p.write_bytes(b'')
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assert crc32_file(str(p)) == 0x00000000
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def test_known_sequence(self, tmp_path):
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"""CRC-32/ISO-HDLC of b'123456789' = 0xCBF43926 (well-known vector)."""
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p = tmp_path / "seq.bin"
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p.write_bytes(b'123456789')
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assert crc32_file(str(p)) == 0xCBF43926
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def test_deterministic(self, tmp_path):
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"""Same file produces same result on repeated calls."""
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p = tmp_path / "data.bin"
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p.write_bytes(b'\xDE\xAD\xBE\xEF' * 256)
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assert crc32_file(str(p)) == crc32_file(str(p))
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def test_single_bit_flip(self, tmp_path):
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"""Flipping one bit changes the CRC."""
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p0 = tmp_path / "d0.bin"
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p1 = tmp_path / "d1.bin"
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p0.write_bytes(b'\x00' * 64)
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p1.write_bytes(b'\x01' + b'\x00' * 63)
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assert crc32_file(str(p0)) != crc32_file(str(p1))
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def test_result_is_uint32(self, tmp_path):
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"""Result fits in 32 bits."""
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p = tmp_path / "rnd.bin"
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p.write_bytes(bytes(range(256)))
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result = crc32_file(str(p))
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assert 0 <= result <= 0xFFFFFFFF
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# ── CRC-32/MPEG-2 (stm32_crc32) ───────────────────────────────────────────
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class TestStm32Crc32:
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def test_result_is_uint32(self):
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assert 0 <= stm32_crc32(b'\x00\x00\x00\x00') <= 0xFFFFFFFF
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def test_deterministic(self):
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data = b'\xDE\xAD\xBE\xEF' * 256
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assert stm32_crc32(data) == stm32_crc32(data)
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def test_avalanche(self):
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d0 = b'\x00' * 256
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d1 = b'\x01' + b'\x00' * 255
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assert stm32_crc32(d0) != stm32_crc32(d1)
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def test_differs_from_iso_hdlc(self):
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"""MPEG-2 and ISO-HDLC produce different results for non-trivial input."""
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data = b'\x01\x02\x03\x04' * 64
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iso = binascii.crc32(data) & 0xFFFFFFFF
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mpeg = stm32_crc32(data)
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assert iso != mpeg, "CRC algorithms should differ"
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def test_pads_to_4bytes(self):
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"""Odd-length input padded to 4-byte boundary with 0xFF."""
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assert stm32_crc32(b'\xAA\xBB\xCC') == stm32_crc32(b'\xAA\xBB\xCC\xFF')
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def test_full_flash_consistent(self):
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"""All-0xFF 512 KB (erased flash) produces a consistent result."""
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data = b'\xFF' * FLASH_SIZE
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r1 = stm32_crc32(data)
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r2 = stm32_crc32(data)
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assert r1 == r2
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assert 0 <= r1 <= 0xFFFFFFFF
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def test_512kb_multiple_of_4(self):
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"""Flash size is a multiple of 4 (no padding needed for full image)."""
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assert FLASH_SIZE % 4 == 0
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def test_different_data_different_crc(self):
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"""Two distinct 4-byte words produce different CRC."""
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a = stm32_crc32(b'\x00\x00\x00\x00')
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b = stm32_crc32(b'\xFF\xFF\xFF\xFF')
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assert a != b
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def test_word_endian_sensitivity(self):
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"""Byte ordering within a 32-bit word affects the result."""
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le_word = struct.pack('<I', 0xDEADBEEF) # EF BE AD DE in memory
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be_word = struct.pack('>I', 0xDEADBEEF) # DE AD BE EF in memory
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assert stm32_crc32(le_word) != stm32_crc32(be_word)
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# ── CRC-16/XMODEM (_crc16_xmodem) ─────────────────────────────────────────
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class TestCrc16Xmodem:
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def test_empty(self):
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"""CRC16 of empty input = 0x0000."""
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assert _crc16_xmodem(b'') == 0x0000
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def test_known_vector(self):
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"""CRC-16/XMODEM of b'123456789' = 0x31C3 (well-known vector)."""
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assert _crc16_xmodem(b'123456789') == 0x31C3
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def test_single_heartbeat_byte(self):
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"""CRC of HEARTBEAT command byte (0x01) is deterministic and non-zero."""
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r = _crc16_xmodem(bytes([0x01]))
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assert isinstance(r, int)
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assert 0 <= r <= 0xFFFF
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assert r != 0
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def test_dfu_cmd_byte(self):
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"""CRC of DFU_ENTER command byte (0x06) is within 16-bit range."""
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r = _crc16_xmodem(bytes([0x06]))
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assert 0 <= r <= 0xFFFF
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def test_deterministic(self):
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data = b'\xCA\xFE\xBA\xBE'
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assert _crc16_xmodem(data) == _crc16_xmodem(data)
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def test_avalanche(self):
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assert _crc16_xmodem(b'\x00') != _crc16_xmodem(b'\x01')
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def test_two_byte_differs_from_one_byte(self):
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"""CRC of two-byte input differs from single-byte input."""
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assert _crc16_xmodem(bytes([0x06, 0x00])) != _crc16_xmodem(bytes([0x06]))
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# ── DFU_ENTER frame structure ──────────────────────────────────────────────
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JLINK_CMD_DFU_ENTER = 0x06
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JLINK_CMD_HEARTBEAT = 0x01
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JLINK_CMD_ESTOP = 0x07
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class TestDfuEnterFrame:
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def test_cmd_id(self):
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"""JLINK_CMD_DFU_ENTER is 0x06 (between PID_SET=0x05 and ESTOP=0x07)."""
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assert JLINK_CMD_DFU_ENTER == 0x06
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def test_cmd_id_between_pid_and_estop(self):
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assert JLINK_CMD_DFU_ENTER > 0x05 # > PID_SET
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assert JLINK_CMD_DFU_ENTER < JLINK_CMD_ESTOP
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def test_frame_length(self):
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"""DFU_ENTER frame = 6 bytes: STX LEN CMD CRC_hi CRC_lo ETX."""
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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assert len(frame) == 6
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def test_frame_stx(self):
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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assert frame[0] == 0x02
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def test_frame_etx(self):
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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assert frame[-1] == 0x03
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def test_frame_len_byte(self):
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"""LEN byte = 1 (CMD only, no payload)."""
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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assert frame[1] == 1
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def test_frame_cmd_byte(self):
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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assert frame[2] == JLINK_CMD_DFU_ENTER
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def test_frame_crc_valid(self):
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"""Embedded CRC validates against CMD byte."""
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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cmd_byte = frame[2]
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crc_hi = frame[3]
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crc_lo = frame[4]
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expected = _crc16_xmodem(bytes([cmd_byte]))
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assert (crc_hi << 8 | crc_lo) == expected
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def test_frame_differs_from_heartbeat(self):
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"""DFU_ENTER frame is distinct from HEARTBEAT frame."""
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assert (_build_jlink_frame(JLINK_CMD_DFU_ENTER) !=
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_build_jlink_frame(JLINK_CMD_HEARTBEAT))
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def test_frame_differs_from_estop(self):
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assert (_build_jlink_frame(JLINK_CMD_DFU_ENTER) !=
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_build_jlink_frame(JLINK_CMD_ESTOP))
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def test_no_payload(self):
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"""DFU_ENTER frame has no payload bytes between CMD and CRC."""
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frame = _build_jlink_frame(JLINK_CMD_DFU_ENTER)
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# Layout: STX LEN CMD [no payload here] CRC_hi CRC_lo ETX
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assert len(frame) == 6 # STX(1)+LEN(1)+CMD(1)+CRC(2)+ETX(1)
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# ── Safety / constants ─────────────────────────────────────────────────────
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class TestOtaConstants:
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def test_dfu_magic(self):
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"""DFU magic = 0xDEADBEEF (Betaflight-proven pattern)."""
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OTA_DFU_MAGIC = 0xDEADBEEF
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assert OTA_DFU_MAGIC == 0xDEADBEEF
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def test_dfu_magic_fits_uint32(self):
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assert 0 <= 0xDEADBEEF <= 0xFFFFFFFF
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def test_bkp_idx_avoids_bno055(self):
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"""BKP15 does not overlap BNO055 range BKP0–BKP6 (PR #150)."""
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OTA_DFU_BKP_IDX = 15
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BNO055_BKP_RANGE = range(0, 7)
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assert OTA_DFU_BKP_IDX not in BNO055_BKP_RANGE
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def test_bkp_idx_valid_stm32f7(self):
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"""STM32F7 has 32 backup registers (BKP0R–BKP31R)."""
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OTA_DFU_BKP_IDX = 15
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assert 0 <= OTA_DFU_BKP_IDX <= 31
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def test_flash_base(self):
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assert FLASH_BASE == 0x08000000
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def test_flash_size_512k(self):
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assert FLASH_SIZE == 512 * 1024
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def test_flash_size_word_aligned(self):
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assert FLASH_SIZE % 4 == 0
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def test_dfu_vid_stmicro(self):
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"""Default VID = 0x0483 (STMicroelectronics)."""
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assert DFU_VID == 0x0483
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def test_dfu_pid_dfu_mode(self):
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"""Default PID = 0xDF11 (STM32 DFU mode)."""
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assert DFU_PID == 0xDF11
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def test_bkp_idx_not_zero(self):
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"""BKP15 ≠ 0 — the old request_bootloader() used BKP0R."""
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assert 15 != 0
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