sl-mechanical
a2c554c232
- docs/: rewrite AGENTS.md, wiring-diagram.md (SAUL-TEE arch); update SALTYLAB.md, FACE_LCD_ANIMATION.md, board-viz.html, SALTYLAB-DETAILED refs - cad/: dimensions.scad FC params → ESP32-S3 BALANCE params - chassis/: ASSEMBLY.md, BOM.md, ip54_BOM.md, *.scad — FC_MOUNT_SPACING/ FC_PITCH → TBD ESP32-S3; Drone FC → MCU mount throughout - CLAUDE.md, TEAM.md: project desc → SAUL-TEE; hardware table → ESP32-S3/VESC - USB_CDC_BUG.md: marked ARCHIVED (legacy STM32 era) - AUTONOMOUS_ARMING.md: USB CDC → inter-board UART (ESP32-S3 BALANCE) - projects/saltybot/SLAM-SETUP-PLAN.md: FC/STM32F722 → BALANCE/CAN - jetson/docs/pinout.md, power-budget.md, README.md: STM32 bridge → CAN bridge - jetson/config/RECOVERY_BEHAVIORS.md: FC+Hoverboard → BALANCE+VESC - jetson/ros2_ws: stm32_protocol.py → esp32_protocol.py, stm32_cmd_node.py → esp32_cmd_node.py, mamba_protocol.py → balance_protocol.py; can_bridge_node imports updated - scripts/flash_firmware.py: DFU/STM32 → pio run -t upload - src/ include/: ARCHIVED headers added (legacy code preserved) - test/: ARCHIVED notices; STM32F722 comments marked LEGACY - ui/diagnostics_panel.html: Board/STM32 → ESP32-S3 Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/* ARCHIVED: Legacy STM32F722/Mamba F722S era code. NOT used in current hardware. */
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#ifndef OTA_H
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#define OTA_H
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#include <stdint.h>
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#include <stdbool.h>
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/*
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* OTA firmware update — Issue #124
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*
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* DFU entry triggered by JLINK_CMD_DFU_ENTER (0x06) or USB CDC 'R' command.
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* Uses RTC backup register OTA_DFU_BKP_IDX to pass magic across the soft reset.
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*
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* RTC BKP register map:
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* BKP0R–BKP5R : BNO055 calibration offsets (PR #150)
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* BKP6R : BNO055 magic (0xB055CA10, PR #150)
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* BKP7R–BKP14R : Reserved
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* BKP15R : OTA DFU magic (this module)
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*
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* Using BKP15R avoids collision with BNO055 (BKP0–6) and the old BKP0R
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* that the original request_bootloader() used before this module.
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*
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* Dual-bank note: STM32F722 has single-bank flash (512 KB). Hardware A/B
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* rollback is not supported without a custom bootloader. DFU via the ST
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* system bootloader at 0x1FF00000 is the supported update path. Rollback
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* is handled by the host-side flash_firmware.py script, which keeps a
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* backup of the previous binary.
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*/
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/* RTC backup register index used for DFU magic — avoids BNO055 BKP0–6 */
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#define OTA_DFU_BKP_IDX 15u
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/* Magic value written before reset to trigger DFU entry on next boot */
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#define OTA_DFU_MAGIC 0xDEADBEEFu
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/* STM32F722 internal flash: 512 KB starting at 0x08000000 */
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#define OTA_FLASH_BASE 0x08000000u
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#define OTA_FLASH_SIZE 0x00080000u /* 512 KB */
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/*
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* ota_enter_dfu(is_armed)
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*
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* Request entry to USB DFU mode (ST system bootloader at 0x1FF00000).
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* Returns false without side effects if is_armed is true.
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* Otherwise: enables backup domain, writes OTA_DFU_MAGIC to BKP15R,
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* disables IRQs, calls NVIC_SystemReset(). Never returns on success.
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*
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* Call from the main loop only (not from ISR context).
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*/
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bool ota_enter_dfu(bool is_armed);
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/*
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* ota_fw_crc32()
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*
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* Compute a CRC-32/MPEG-2 checksum of the full flash region using the
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* STM32 hardware CRC peripheral (poly 0x04C11DB7, init 0xFFFFFFFF,
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* 32-bit words, no reflection). Covers OTA_FLASH_SIZE bytes from
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* OTA_FLASH_BASE including erased padding.
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*
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* Takes ~0.5 ms at 216 MHz. Call only while disarmed.
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*/
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uint32_t ota_fw_crc32(void);
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#endif /* OTA_H */
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