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Stack Connector and Addressing
blue edited this page 2026-06-11 15:02:38 -04:00

Resound — Stack Connector, Bus & I2C Addressing

Physical/electrical interconnect for the stackable unit (1 SINK + N BROADCASTERS of identical ESP32-WROOM, + ESP32-S3 HUD). Audio 44.1k/16/stereo -> BCK = 1.4112 MHz.

1. Stacking connector

26-pin (2x13) 2.54 mm THT pass-through stacking header, polarized/keyed, ~3 A/pin (vibration-rated), 11-12 mm board pitch (clears the WROOM can). Pass-through tails let identical boards self-nest into a vertical bus column with no orientation flip. (Samtec Flex-Stacking pass-through / SSQ-elevated, or Amphenol BergStik stack-through.) THT over fine-pitch SMT for vibration pull-out strength; bus speeds are low so no controlled-impedance needed.

Pinout (grounds bracket the I2S clock/data for return current):

Pin Sig Pin Sig
1 5V 2 5V
3 GND 4 GND
5 3V3 6 3V3
7 GND 8 I2S_BCK
9 GND 10 I2S_WS
11 GND 12 I2S_DATA
13 GND 14 GND
15 I2C_SDA 16 I2C_SCL
17 UART1_TX 18 UART1_RX
19 UART2_TX 20 UART2_RX
21 LED_DAT 22 LED_CLK (APA102)
23 ADDR_CHAIN_IN 24 ADDR_CHAIN_OUT
25 SPARE0 26 GND

(LED is APA102 -> two lines DATA+CLK, per the LED page; if a board's bus pins 23/24 are reused for chain auto-enum they must not be the I2C pins.)

2. Mechanical stack

WROOM-up identical boards; M3 corner standoffs carry the vibration load (connector contacts aren't structural). SINK at bottom (owns I2S master + power entry); broadcasters stack above; HUD ribbon-attached on top facing the rider (needs only I2C+5V+GND). Each board has a local 3V3 buck/LDO — don't bus regulated 3V3 across 6-12 boards (IR drop). 5V bussed on the two paralleled pins (~6 A).

Scale to 6/12 via a passive backplane carrying the bus to several vertical sockets (e.g. 4x3 = 12), with the ADDR chain routed serially stack->stack for deterministic addressing, and I2S distributed as a buffered star (one branch per stack column) — never one tall column past ~4 boards.

3. I2C addressing (identical boards/firmware)

SINK fixed (0x08); broadcasters 0x10..0x1B (up to 12).

  • Recommended v1: 4-bit straps on input-only/safe GPIOs read at boot -> addr = 0x10 | nibble. Vibration-proof, supports 16. (NOTE: this system's I2C is on GPIO32/33 per firmware, so straps live on other safe pins e.g. 13/14/27/26; the connector's ADDR_CHAIN pins must avoid 32/33.)
  • Scale-up: GPIO daisy-chain auto-enumeration — each board claims the next address by physical position (zero config). Firmware: hold next board's CHAIN_OUT low, wait for CHAIN_IN, claim next index from SINK over I2C, release upward. Elegant for many identical boards; needs a boot handshake + timeout fallback to straps for bench use.

4. Signal integrity

  • I2S (1.41 MHz @44.1k, 2.82 @48k): don't drive up to 12 inputs from one GPIO. Buffer at the SINK (74LVC125/2G34) + 22-33 R series term per line, star fan-out (one branch/stack). Medium GPIO drive (not max — high drive into a capacitive stub network increases ringing). Grounds bracket BCK/WS/DATA through every connector.
  • I2C: up to ~14-16 nodes; keep bus < 400 pF. Run 100 kHz with a single 2.2 kOhm pull-up pair at the HUD/SINK (Fast-mode 400 kHz isn't safely achievable across a fully-loaded 12-board bus on one pull-up — the R_min/R_max window closes). For 12 boards/higher speed add a PCA9548A mux or P82B96 buffer per stack. One pull-up set only; every other board taps open-drain.

Sources

Samtec Flex-Stacking pass-through + design guide + SSQ; Amphenol BergStik 2.54 stacking; TE board-to-board / Micro-MaTch; ESP-IDF I2S (clock, drive strength); FluidNC signal-quality (edges/termination); AllAboutCircuits + TotalPhase I2C pull-up math; ESP32 GPIO/strapping reference.