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2c6e7e8762
Netlist-first KiCad-import package for the single carrier PCB (ESP32-WROOM-32E, SINK/BROADCASTER assembly variants): - hardware/carrier/resound-carrier.net : KiCad s-expr netlist, 44 components / 40 nets, real library footprints (RF_Module:ESP32-WROOM-32, 2x13 stacking header, 0402 passives, SOT-23 auto-reset, JST-SH HUD conn). Parens balanced. - hardware/carrier/BOM.csv : 44 parts (ref/value/footprint/MPN/DNP/notes). - hardware/carrier/LAYOUT.md : 45x45 4-layer stackup, 15mm antenna keep-out, placement, JLCPCB DRC, SINK-vs-BROADCASTER variant + address-strap table. - hardware/carrier/README.md : KiCad import steps + caveats. Agent decisions flagged for EE: LED moved off the GPIO13 strap to LED_DAT=GPIO21 / LED_CLK=GPIO4; verify WROOM footprint pad numbering; UART2 is connector-only this rev. Deliverable is import-ready netlist+BOM+spec, not a finished .kicad_pcb. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
130 lines
7.3 KiB
Markdown
130 lines
7.3 KiB
Markdown
# Resound Small Build — Carrier PCB Layout & Fab Spec
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This document is the layout intent that pairs with `resound-carrier.net`. The netlist
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defines connectivity; this defines board outline, stackup, placement, and design rules.
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An engineer imports the netlist into KiCad, then lays out per the constraints here.
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## 1. Board outline
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- **Size:** 45.0 mm x 45.0 mm.
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- **Corners:** rounded, R = 3.0 mm (4x).
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- **Edge.Cuts** layer defines outline. Keep all copper >= 0.3 mm inside the edge except
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the deliberate antenna keep-out region (see section 4).
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## 2. Stackup (4-layer)
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| Layer | Name | Use |
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|-------|-------------|--------------------------------------------------|
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| L1 | Sig (top) | Components, signal routing, WROOM, connectors |
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| L2 | GND | Solid ground plane (reference for all signals) |
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| L3 | PWR | +3V3 / +5V power pours |
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| L4 | Sig (bottom)| Signal routing, bottom stacking header, fanout |
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- Standard JLCPCB 4-layer: 1.6 mm finished, 0.5 oz inner / 1 oz outer, FR-4 TG155 OK.
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- Stitch GND plane to top/bottom ground pours with vias around board perimeter and under
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the WROOM ground pad array. Place a dense via field under U1's exposed/edge GND pads.
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## 3. Power distribution
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- +5V enters on stacking connector J1 pins 1,2. C8 (10uF) bulk at connector.
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- +3V3 rail on J1 pins 5,6 (module/regulator assumed upstream on the +3V3 supplying board).
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C9 (22uF) bulk on 3V3. C5 (10uF) + C6/C7 (100nF) directly at the WROOM 3V3 pad (pad 2),
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shortest possible loop to nearest GND via.
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- Power pour widths: 5V and 3V3 main feeds >= 0.6 mm or plane on L3.
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## 4. Antenna keep-out (CRITICAL)
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- U1 (ESP32-WROOM-32E) placed at one board edge with the **PCB antenna overhanging the
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board edge** — the antenna end of the module must sit flush with / past the edge cut.
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- **15 mm copper keep-out, ALL LAYERS**, around the antenna: no copper (no traces, no
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pours, no plane fill, no ground) within 15 mm of the antenna trace footprint, including
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L2 GND and L3 PWR planes. Add a keep-out zone on every layer.
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- No mounting hardware, no metal, no components in the antenna keep-out.
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- This is why U1 lives at the edge and the antenna overhangs: maximize RF clearance.
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## 5. Placement plan
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```
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+-----------------------------------------------+
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| (H1) (H2) |
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| [ U1 ESP32-WROOM-32E ] <- antenna overhang| <- this edge: antenna keep-out 15mm
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| 3V3 decap C5/C6/C7 hugging pad 2 |
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| [ J1 2x13 stacking connector ] | <- centered, vertical, top+bottom
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| I2S jumper field JP1..JP6 near J1 |
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| [J2 prog 1x6] Q1 Q2 C3 C4 [SW1] [SW2] | <- opposite edge: prog + buttons
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| (H3) [J3 HUD SH1.0 - TOP only] (H4) |
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+-----------------------------------------------+
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```
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- **U1:** top edge, antenna overhanging, keep-out enforced.
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- **J1 stacking connector:** centered on the board so the stack aligns mechanically.
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Top header + mirrored bottom header on the SAME footprint position share nets
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(pass-through). Verify pin 1 indexing matches between top and bottom of the stack.
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- **I2S role jumpers JP1..JP6:** group as two visible columns (SINK | BROADCASTER) next
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to J1, silkscreen-label each column and net.
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- **Address straps R10..R17:** group as a labelled field; silkscreen "3V3 / GND" per strap.
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- **Prog header J2, transistors Q1/Q2, caps C3/C4, buttons SW1/SW2:** opposite edge from
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the antenna, accessible.
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- **J3 HUD SH1.0:** near a board edge, TOP board assembly only.
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- **Mounting holes H1..H4:** 38 x 38 mm square pattern (centered on 45x45 board => holes
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at +/-19 mm from center X and Y), M3 (3.2 mm), keep clear of antenna keep-out (move the
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two antenna-edge holes inward if they fall inside the 15 mm keep-out).
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## 6. Design rules (JLCPCB 4-layer, standard)
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- Min trace width: 0.127 mm (5 mil); use 0.2 mm default signal, 0.15 mm only in fanout.
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- Min spacing: 0.127 mm (5 mil); 0.2 mm default.
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- Min via: 0.3 mm drill / 0.6 mm pad; 0.2/0.4 only where needed.
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- Min annular ring: 0.13 mm.
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- Edge clearance: copper >= 0.3 mm from Edge.Cuts (except antenna keep-out which is larger).
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- **I2S series termination:** R1/R2/R3 (33R) footprints sit inline on I2S_BCK/WS/DATA
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between the jumper field and J1. Default DNP — if I2S edges ring on the scope across the
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stack, populate 33R and remove the equivalent direct short. Keep I2S traces short, equal
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length within the pair set, referenced to L2 GND, away from the antenna.
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- **Single pull-up rule:** I2C SDA/SCL pull-ups (R4/R5) have footprints on EVERY board but
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are DNP except on the SINK board, so the bus has exactly ONE pull-up pair across the stack.
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- Decoupling caps: place on the same layer as U1, vias to L2/L3 directly under the cap pad.
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## 7. Assembly variants (ONE board, two BOMs)
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| Item / Net | SINK board | BROADCASTER board |
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|-----------------------|----------------------------|----------------------------|
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| I2S BCK jumper | JP1 (GPIO5) populated | JP4 (GPIO19) populated |
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| I2S WS jumper | JP2 (GPIO25) populated | JP5 (GPIO18) populated |
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| I2S DATA jumper | JP3 (GPIO23) populated | JP6 (GPIO22) populated |
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| Opposite I2S column | JP4/JP5/JP6 DNP | JP1/JP2/JP3 DNP |
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| I2C pull-up R4 (SDA) | **populate 4.7k** | DNP |
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| I2C pull-up R5 (SCL) | **populate 4.7k** | DNP |
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| I2S series term R1-R3 | DNP (unless ringing) | DNP (unless ringing) |
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| HUD connector J3 | per mechanical (TOP only) | per mechanical (TOP only) |
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| Address straps | per node address (see below)| per node address |
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| Reset/boot/prog (R6-9, C1-4, Q1-2, SW1-2, J2) | populate | populate |
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| Decoupling C5-C9 | populate | populate |
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**Address straps (R10..R17):** for each of ADDR0..ADDR3, populate EXACTLY ONE of the pair:
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- "1" / high => populate the 10k-to-3V3 resistor (R10/R12/R14/R16), leave the 0R-to-GND DNP.
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- "0" / low => populate the 0R-to-GND resistor (R11/R13/R15/R17), leave the 10k DNP.
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This is independent of SINK/BROADCASTER — it sets each board's bus address in the stack.
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## 8. Connector pinouts (reference)
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### J1 — 26-pin (2x13) stacking, 2.54 mm, pass-through (top + mirrored bottom)
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| Pin | Net | Pin | Net |
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|-----|------------|-----|------------|
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| 1 | +5V | 2 | +5V |
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| 3 | GND | 4 | GND |
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| 5 | +3V3 | 6 | +3V3 |
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| 7 | GND | 8 | I2S_BCK |
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| 9 | GND | 10 | I2S_WS |
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| 11 | GND | 12 | I2S_DATA |
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| 13 | GND | 14 | GND |
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| 15 | I2C_SDA | 16 | I2C_SCL |
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| 17 | UART_TX | 18 | UART_RX |
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| 19 | UART2_TX | 20 | UART2_RX |
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| 21 | LED_DAT | 22 | LED_CLK |
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| 23 | ADDR_CHAIN_IN | 24 | ADDR_CHAIN_OUT |
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| 25 | SPARE | 26 | GND |
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### J2 — programming 1x6, 2.54 mm
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1=GND, 2=+5V, 3=RX (IO3 / GPIO3), 4=TX (IO1 / GPIO1), 5=DTR, 6=RTS
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### J3 — HUD SH1.0 1x6 (TOP board only)
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1=+5V (VSYS), 2=GND, 3=I2C_SDA, 4=I2C_SCL, 5=SPARE, 6=NC
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(Verify physical pin order against the HUD cable before fab — see README caveat.)
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