blue-repeat/hardware/carrier/LAYOUT.md

Resound Small Build — Carrier PCB Layout & Fab Spec

This document is the layout intent that pairs with resound-carrier.net. The netlist defines connectivity; this defines board outline, stackup, placement, and design rules. An engineer imports the netlist into KiCad, then lays out per the constraints here.

1. Board outline

• Size: 45.0 mm x 45.0 mm.
• Corners: rounded, R = 3.0 mm (4x).
• Edge.Cuts layer defines outline. Keep all copper >= 0.3 mm inside the edge except the deliberate antenna keep-out region (see section 4).

2. Stackup (4-layer)

Layer	Name	Use
L1	Sig (top)	Components, signal routing, WROOM, connectors
L2	GND	Solid ground plane (reference for all signals)
L3	PWR	+3V3 / +5V power pours
L4	Sig (bottom)	Signal routing, bottom stacking header, fanout

• Standard JLCPCB 4-layer: 1.6 mm finished, 0.5 oz inner / 1 oz outer, FR-4 TG155 OK.
• Stitch GND plane to top/bottom ground pours with vias around board perimeter and under the WROOM ground pad array. Place a dense via field under U1's exposed/edge GND pads.

3. Power distribution

• +5V enters on stacking connector J1 pins 1,2. C8 (10uF) bulk at connector.
• +3V3 rail on J1 pins 5,6 (module/regulator assumed upstream on the +3V3 supplying board). C9 (22uF) bulk on 3V3. C5 (10uF) + C6/C7 (100nF) directly at the WROOM 3V3 pad (pad 2), shortest possible loop to nearest GND via.
• Power pour widths: 5V and 3V3 main feeds >= 0.6 mm or plane on L3.

4. Antenna keep-out (CRITICAL)

• U1 (ESP32-WROOM-32E) placed at one board edge with the PCB antenna overhanging the board edge — the antenna end of the module must sit flush with / past the edge cut.
• 15 mm copper keep-out, ALL LAYERS, around the antenna: no copper (no traces, no pours, no plane fill, no ground) within 15 mm of the antenna trace footprint, including L2 GND and L3 PWR planes. Add a keep-out zone on every layer.
• No mounting hardware, no metal, no components in the antenna keep-out.
• This is why U1 lives at the edge and the antenna overhangs: maximize RF clearance.

5. Placement plan

   +-----------------------------------------------+
   | (H1)                                    (H2)  |
   |   [ U1  ESP32-WROOM-32E ]  <- antenna overhang|  <- this edge: antenna keep-out 15mm
   |   3V3 decap C5/C6/C7 hugging pad 2            |
   |                                               |
   |        [ J1  2x13 stacking connector ]        |  <- centered, vertical, top+bottom
   |        I2S jumper field JP1..JP6 near J1      |
   |                                               |
   |  [J2 prog 1x6]   Q1 Q2 C3 C4   [SW1] [SW2]    |  <- opposite edge: prog + buttons
   | (H3)   [J3 HUD SH1.0 - TOP only]        (H4)  |
   +-----------------------------------------------+

• U1: top edge, antenna overhanging, keep-out enforced.
• J1 stacking connector: centered on the board so the stack aligns mechanically. Top header + mirrored bottom header on the SAME footprint position share nets (pass-through). Verify pin 1 indexing matches between top and bottom of the stack.
• I2S role jumpers JP1..JP6: group as two visible columns (SINK | BROADCASTER) next to J1, silkscreen-label each column and net.
• Address straps R10..R17: group as a labelled field; silkscreen "3V3 / GND" per strap.
• Prog header J2, transistors Q1/Q2, caps C3/C4, buttons SW1/SW2: opposite edge from the antenna, accessible.
• J3 HUD SH1.0: near a board edge, TOP board assembly only.
• Mounting holes H1..H4: 38 x 38 mm square pattern (centered on 45x45 board => holes at +/-19 mm from center X and Y), M3 (3.2 mm), keep clear of antenna keep-out (move the two antenna-edge holes inward if they fall inside the 15 mm keep-out).

6. Design rules (JLCPCB 4-layer, standard)

• Min trace width: 0.127 mm (5 mil); use 0.2 mm default signal, 0.15 mm only in fanout.
• Min spacing: 0.127 mm (5 mil); 0.2 mm default.
• Min via: 0.3 mm drill / 0.6 mm pad; 0.2/0.4 only where needed.
• Min annular ring: 0.13 mm.
• Edge clearance: copper >= 0.3 mm from Edge.Cuts (except antenna keep-out which is larger).
• I2S series termination: R1/R2/R3 (33R) footprints sit inline on I2S_BCK/WS/DATA between the jumper field and J1. Default DNP — if I2S edges ring on the scope across the stack, populate 33R and remove the equivalent direct short. Keep I2S traces short, equal length within the pair set, referenced to L2 GND, away from the antenna.
• Single pull-up rule: I2C SDA/SCL pull-ups (R4/R5) have footprints on EVERY board but are DNP except on the SINK board, so the bus has exactly ONE pull-up pair across the stack.
• Decoupling caps: place on the same layer as U1, vias to L2/L3 directly under the cap pad.

7. Assembly variants (ONE board, two BOMs)

Item / Net	SINK board	BROADCASTER board
I2S BCK jumper	JP1 (GPIO5) populated	JP4 (GPIO19) populated
I2S WS jumper	JP2 (GPIO25) populated	JP5 (GPIO18) populated
I2S DATA jumper	JP3 (GPIO23) populated	JP6 (GPIO22) populated
Opposite I2S column	JP4/JP5/JP6 DNP	JP1/JP2/JP3 DNP
I2C pull-up R4 (SDA)	populate 4.7k	DNP
I2C pull-up R5 (SCL)	populate 4.7k	DNP
I2S series term R1-R3	DNP (unless ringing)	DNP (unless ringing)
HUD connector J3	per mechanical (TOP only)	per mechanical (TOP only)
Address straps	per node address (see below)	per node address
Reset/boot/prog (R6-9, C1-4, Q1-2, SW1-2, J2)	populate	populate
Decoupling C5-C9	populate	populate

Address straps (R10..R17): for each of ADDR0..ADDR3, populate EXACTLY ONE of the pair:

• "1" / high => populate the 10k-to-3V3 resistor (R10/R12/R14/R16), leave the 0R-to-GND DNP.
• "0" / low => populate the 0R-to-GND resistor (R11/R13/R15/R17), leave the 10k DNP.

This is independent of SINK/BROADCASTER — it sets each board's bus address in the stack.

8. Connector pinouts (reference)

J1 — 26-pin (2x13) stacking, 2.54 mm, pass-through (top + mirrored bottom)

Pin	Net	Pin	Net
1	+5V	2	+5V
3	GND	4	GND
5	+3V3	6	+3V3
7	GND	8	I2S_BCK
9	GND	10	I2S_WS
11	GND	12	I2S_DATA
13	GND	14	GND
15	I2C_SDA	16	I2C_SCL
17	UART_TX	18	UART_RX
19	UART2_TX	20	UART2_RX
21	LED_DAT	22	LED_CLK
23	ADDR_CHAIN_IN	24	ADDR_CHAIN_OUT
25	SPARE	26	GND

J2 — programming 1x6, 2.54 mm

1=GND, 2=+5V, 3=RX (IO3 / GPIO3), 4=TX (IO1 / GPIO1), 5=DTR, 6=RTS

J3 — HUD SH1.0 1x6 (TOP board only)

1=+5V (VSYS), 2=GND, 3=I2C_SDA, 4=I2C_SCL, 5=SPARE, 6=NC (Verify physical pin order against the HUD cable before fab — see README caveat.)